Yosys-backed synthesis · Gate-level STA · In-browser

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Compile multi-file RTL projects into interactive gate schematics. Hierarchy-preserving submodule blocks, real vector bus collapsing, and on-demand gate-level timing analysis with per-process-node estimation — no install, no license, right in your browser.

▷ Launch RTL Bench

audio_soc_top.sv ⇄ hybrid → flat → timing analysis

module audio_soc_top (
  input logic clk, rst_n,
  output logic audio_out,
  output logic [7:0] gpio_pins
);
  // Hierarchy → flattened netlist
  // → gate-level timing analysis
  cpu_top     u_cpu       (.clk(clk));
  axi_router   u_bus_router (.m_axi(...));
  audio_pwm    u_audio     (.sample(...));
  apb_decoder u_apb_dec   (.pclk(clk));
endmodule

3 View Modes

Simple · Hybrid · Detailed — auto-switched by zoom level

Hierarchy + Flat

Dual graph model from a single compile

4 Process Nodes

180 nm · 90 nm · 45 nm · 7 nm for STA

Yosys + ELK

Open-source toolchain, fully in-browser

Engineered for real RTL workflows

Not a diagram toy — every feature maps to a step in an actual synthesis and timing-signoff pipeline.

📁

Multi-file projects with $readmemh

Drop a folder of .sv / .v sources and data files; relative paths are preserved so $readmemh("dv/hex/fw.hex") finds its files. Top module is auto-detected or overridden from a dropdown.

🧩

Hierarchy-preserving synthesis

Submodule instances render as encapsulated blocks with named port pins and input/output direction dots. Toggle Hierarchy to collapse into blocks, or Flat to unroll every gate — from the same compile.

⏱

Gate-level static timing analysis

Yosys techmap decomposes the design to real gates, then the longest structural path is measured as gate depth. Per-process-node conversion (180/90/45/7 nm) gives a nanosecond estimate with top-K critical paths and a cell-by-cell breakdown.

🔍

Semantic LOD zooming

No dropdown to switch views — the tool watches your zoom and cross-fades between macro block diagrams and detailed gate schematics. Submodule boxes reveal their internals as you zoom in past a threshold.

🧵

Vector bus collapsing

Bit-blasted Yosys nets are regrouped into single vector wires with IEEE /W slash notation and a width label. Branch fan-out is drawn with proper solder dots, so wide datapaths stay legible.

🔗

Fused constant comparators

An == against a literal like 8'hA5 is rendered as a single comparator cell with the value fused into an adjacent chip. No dangling constant wires — the operation reads as one unit.

🖱️

Click-to-trace nets

Every wire is interactive. Click any net to highlight the full routed path across the canvas — from a primary input through combinational logic to a register or output pin. Ideal for tracking feedback loops.

📐

Orthogonal Manhattan routing

Powered by the Eclipse Layout Kernel with edgeRouting: ORTHOGONAL. Wires travel only on horizontal and vertical lanes with clean 90° corners — the same visual convention used by commercial EDA tools.

⤓

Vector SVG export

Export the current view as a clean, resolution-independent SVG — no rasterization, no watermarks. Suitable for design reviews, IEEE figures, or embedding in documentation.

RTL to netlist, in four stages

The pipeline below runs on every compile — the same flow your synthesis toolchain uses.

Upload or paste your RTL

Drop a folder of sources, paste a single file, or pick a preset. Top module and data files are auto-detected.

Yosys RTLIL elaboration

Your source is sandboxed and elaborated by read_verilog → proc → opt → clean. Clocks and resets are inferred automatically.

ELK placement & routing

Eclipse Layout Kernel positions cells in a LEFT→RIGHT layered graph and routes every net with orthogonal Manhattan edges.

Inspect, trace & time

Zoom through the hierarchy, click nets to trace them, run gate-level STA on demand, and export the view as a vector SVG.